Verification of an IP Interface Prototype Design through Simulation and Emulation

Designing contemporary Systems-On-a-Chip (SOCs) introduces increasing complexity and heterogeneity to integrated circuits. Attention has to be paid especially to the interfaces between the reusable Intellectual Property (IP) blocks used in them. We have previously presented our own interface solution called Heterogeneous IP Block Interconnection (HIBI). In this paper, the verification of a HIBI-based IP interface prototype design through simulation and emulation is discussed. The verification of the design is analysed and some performance characteristics from various steps of the verification flow are described. In addition to a significant reduction in compilation times, hardware emulation test runs are found to be hundreds of times faster than ordinary gate-level simulations. Nevertheless, both simulation and emulation were found to be needed in the verification process of modern SOC designs. Key-Words: System-On-a-Chip (SOC), Intellectual Property (IP), IP Interface, Hardware Emulation, Simulation, Verification